In integrated circuits, as electrical signals such as those representing binary digits (i.e., bits) are transmitted from one area to another, noise may be introduced on the transmission path which may alter the electrical signal. For example, a logical high bit (e.g., “1”) sent from a memory controller may be received as a logical low bit (e.g., “0”) at a memory, such as a dynamic random access memory (“DRAM”), if sufficient noise is introduced on the transmission path causing the bit to “flip.” Also, even if no noise is introduced on the transmission path, a bit may be transmitted incorrectly due to other problems, such as errors in the sending or receiving circuits. Incorrectly transmitted bits may cause problems, such as system errors and incorrect memory commands, or such as data being stored incorrectly in a memory.
In order to mitigate the errors associated with incorrectly transmitted bits, error detection and/or error correction codes are often used. For example, a parity bit may be added to a set of bits in order to help detect errors in transmission of the bits. The set of bits may represent, among other things, an address, a command, a number, or other information (e.g., information to be stored in memory), or some combination of these. The set of bits may be referred to as a “word.” A 22-bit word, for example, may include an address and multiple commands in some embodiments. Before the 22-bit word is transmitted, a sending circuit may generate a parity bit by, for example, XORing all of the bits in the word, and may add the parity bit to the word (thus making it 23-bits), usually at the end or at the beginning of the word. The full 23-bit word may then be transmitted.
The added parity bit may be an “even” type (which may be referred to as using even panty), or an “odd” type (which may be referred to as using odd parity). In even parity, the panty bit may be set to a logical high value if the original word (without the parity bit) has an odd number of logical high bits, thereby causing the total number of logical high bits in the word to be even. Causing the total number of logical high bits in a word to be even may facilitate subsequent checking of the word (e.g., after transmission) to determine if any of the bits “flipped” since the parity bit was generated. For example, when the word is received at a receiving circuit, the receiving circuit may check the parity of the received word (which includes the parity bit). If the received word has an even number of logical high bits, the parity of the word is even and thus “correct.” If the received word has an odd number of logical high bits, the parity of the word is odd and thus “incorrect,” which means that at least one bit was transmitted incorrectly.
In odd parity, the parity bit may be set to logical high if the original word (without the parity bit) has an even number of logical high bits, thereby causing the total number of logical high bits in the word to be odd. Words transmitted using odd parity may similarly be checked at a receiving circuit by determining the parity of the word as received.
Although parity bits are not able to correct an incorrectly transmitted bit (because the parity bit cannot tell which bit was transmitted incorrectly), and although they are only able to detect single or other odd numbers of incorrectly transmitted bits (i.e., the parity of the received word will be “correct” if 2, 4, 6, etc. bits are transmitted incorrectly), they are an economical way of detecting some incorrectly transmitted bits. More complex error detection schemes (such as a cyclic redundancy code) may be used when more precision or error correction is needed, although these more complex schemes may require more processing and/or more bandwidth to transfer additional redundancy information.
As the operating frequency of an integrated circuit increases, the incidence of incorrectly transmitted bits may increase. Also, because the clock period shortens as the operating frequency increases, the time during which error detection operations and in some cases error correction operations) need to complete may decrease. Even with a relatively simple error detection code such as a parity bit, the error detection operations may tend to limit the otherwise increasingly fast operating frequency of an integrated circuit, particularly for integrated circuits where a new word may be received every clock cycle (thereby requiring error detection operations to complete every dock cycle). Also, in some integrated circuits, the operating frequency of the circuit may be variable.
It may thus be desirable in some instances to decrease the parity latency (e.g., the amount of time required to check for incorrectly transmitted bits by determining the parity of a transmitted word). It may furthermore be desirable to asynchronously provide signals indicating the parity correctness or incorrectness, in addition to synchronously providing such information.